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CY62167EV30 MoBL(R)
16-Mbit (1M x 16 / 2M x 8) Static RAM
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features

TSOP I package configurable as 1M x 16 or 2M x 8 SRAM Very high speed: 45 ns Temperature ranges Industrial: -40C to +85C Automotive-A: -40C to +85C Wide voltage range: 2.20 V to 3.60 V Ultra-low standby power Typical standby current: 1.5 A Maximum standby current: 12 A Ultra-low active power Typical active current: 2.2 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE Features Automatic power-down when deselected CMOS for optimum speed and power Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I packages

More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the "Truth Table" on page 11 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Design Guidelines.

Functional Description
The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits. This device features an advanced circuit design that provides an ultra low active current. Ultra low active current is ideal for providing
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
DATA IN DRIVERS
1M x 16 / 2M x 8 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
CE2 BYTE BHE WE OE BLE
Power Down Circuit
CE1 BHE BLE
A11 A12 A13 A14 A15 A16 A17 A18 A19
CE2 CE1
Cypress Semiconductor Corporation Document #: 38-05446 Rev. *I
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 13, 2010
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Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings............................................................. 4 Operating Range............................................................... 4 Electrical Characteristics................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance.......................................................... 5 Data Retention Characteristics ....................................... 6 Switching Characteristics................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information...................................................... Ordering Code Definition........................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 12 12 13 14 15 16 16 16 16
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Pin Configuration
Figure 1. 48-Ball VFBGA (6 x 8 x 1mm) Top View [1, 2]
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 I/O12 I/O13 A19 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC Vss I/O6 I/O7 NC A B C D E F G H
Figure 2. 48-Pin TSOP I Top View [2, 3]
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62167EV30LL Industrial/Auto-A 2.2 Typ[4] 3.0 Max 3.6 45 Speed (ns) Typ[4] 2.2 Operating ICC (mA) f = 1 MHz Max 4.0 f = fmax Typ[4] 25 Max 30 Standby ISB2 (A) Typ[4] 1.5 Max 12
Notes 1. Ball H6 for the VFBGA package can be used to upgrade to a 32M density. 2. NC pins are not connected on the die. 3. The BYTE pin in the 48-pin TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-pin TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C.
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ -65C to + 150 C Ambient temperature with power applied .......................................... -55 C to + 125 C Supply voltage to ground potential ..............................-0.3 V to 3.9 V VCC (max) + 0.3 V DC voltage applied to outputs in High Z state[5, 6] ..............-0.3 V to 3.9 V VCC (max) + 0.3 V DC input voltage[5, 6]........ -0.3 V to 3.9 V (VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage........................................... >2001 V (MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA
Operating Range
Device CY62167EV30LL Range Industrial/ Auto-A Ambient Temperature -40 C to +85 C VCC[7] 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA 45 ns (Industrial/Auto-A) Unit Min Typ[8] Max 2.0 - - V 2.4 - - V - - 0.4 V - - 0.4 V 1.8 - VCC + 0.3 V V 2.2 - VCC + 0.3 V V -0.3 - 0.6 V -0.3 - 0.8 V -0.3 - 0.7[9] V -1 - +1 A -1 - +1 A - 25 30 mA - 2.2 4.0 mA - 1.5 12 A
For VFBGA package For TSOP I package
IIX IOZ ICC ISB1
Input leakage current Output leakage current VCC operating supply current Automatic power down current--CMOS inputs
ISB2[10]
Automatic power down current--CMOS inputs
GND < VI < VCC GND < VO < VCC, Output disabled f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC - 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2V, VIN < 0.2 V) f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC (max) CE1 > VCC - 0.2V or CE2 < 0.2 V or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC (max)
-
1.5
12
A
Capacitance
Parameter[11] Description Input capacitance CIN Output capacitance COUT Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 5. VIL(min) = -2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V. This is applicable to TSOP I package only. 10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance
Parameter[12] JA JC Description Test Conditions VFBGA (6 x 8 x 1mm) 55 16 TSOP I 60 4.3 Unit C/W C/W
Thermal resistance Still air, soldered on a 3 x 4.5 inch, (Junction to ambient) two-layer printed circuit board Thermal resistance (Junction to case)
Figure 3. AC Test Loads and Waveforms
VCC OUTPUT R1 VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V
Parameters R1 R2 RTH VTH
2.2 V to 2.7 V 16667 15385 8000 1.20
2.7 V to 3.6 V 1103 1554 645 1.75
Unit V
Note 12. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[14] Description VCC for data retention Data retention current VCC = 1.5 V to 3.0 V, CE1 > VCC - 0.2 V or Industrial CE2 < 0.2 V or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V VCC = 1.5 V, CE1 > VCC - 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V tCDR
[15]
Conditions 48-pin TSOP I Other packages
Min Typ[13] Max Unit 1.5 - - - - 8 V A
Industrial
- - 0 45
- - - -
10 10 - -
A A - ns
Auto-A All packages
Chip deselect to data retention time Operation recovery time Figure 4. Data Retention Waveform VCC
CE1 or
[17]
tR[16]
VCC(min) tCDR
DATA RETENTION MODE VDR > 1.5 V
VCC(min) tR
BHE.BLE
or
CE2
Notes 13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 14. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 15. Tested initially and after any design or process changes that may affect these parameters. 16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 17. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
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Switching Characteristics
Parameter[18, 19] READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[22]
Description
45 ns (Industrial/Auto-A) Min 45 - 10 - - 5 - 10 - 0 - - 10 - 45 35 35 0 0 35 35 25 0 - 10 Max - 45 - 45 22 - 18 - 18 - 45 45 - 18 - - - - - - - - - 18 -
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to LOW Z
[20] [20, 21]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z
CE1 LOW and CE2 HIGH to Low Z[20] CE1 HIGH and CE2 LOW to High Z[20, 21] CE1 LOW and CE2 HIGH to power-up CE1 HIGH and CE2 LOW to power-down BLE / BHE LOW to data valid BLE / BHE LOW to Low Z[20] Z[20, 21] BLE / BHE HIGH to HIGH Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE / BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High Z WE HIGH to Low Z
[20, 21] [20]
Notes 18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in "AC Test Loads and Waveforms" on page 5. 19. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 21. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 22. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[23, 24]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[24, 25]
ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE
Notes 23. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 24. WE is HIGH for read cycle. 25. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
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Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled)[26, 27, 28]
tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 29 tHZOE VALID DATA
tHD
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled)[26, 28]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE DATA I/O NOTE 29
tSD VALID DATA
tHD
tHZOE Notes 26. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write 27. Data I/O is high impedance if OE = VIH. 28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 29. During this period the I/Os are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW)[30]
tWC ADDRESS tSCE CE1 CE2
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA I/O NOTE 31 VALID DATA
tHD
tHZWE
tLZWE
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[30]
tWC ADDRESS
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 31 VALID DATA tHD tBW tHA
Notes 30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 31. During this period the I/Os are in output state. Do not apply input signals.
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Truth Table
CE1 H X[32] X
[32]
CE2 X[32] L X
[32]
WE X X X H H H H H H L L L
OE X X X L L L H H H X X X
BHE BLE X X H L H L L H L L H L X X H L L H H L L L L H
Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data Out (I/O8-I/O15) High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data In (I/O8-I/O15)
Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output disabled Output disabled Output disabled Write Write Write
Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
L L L L L L L L L
H H H H H H H H H
Note 32. The `X' (Don't care) state for the chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted
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CY62167EV30 MoBL(R)
Ordering Information
Speed (ns) 45 Ordering Code CY62167EV30LL-45BVI CY62167EV30LL-45BVXI CY62167EV30LL-45ZXI CY62167EV30LL-45BVXA CY62167EV30LL-45ZXA Package Diagram 51-85150 51-85150 51-85183 51-85150 51-85183 Package Type 48-ball VFBGA (6 x 8 x 1 mm) 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free) 48-pin TSOP I (Pb-free) 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free) 48-pin TSOP I (Pb-free) Automotive-A Operating Range Industrial
Ordering Code Definition
CY 621 6 7 E V30 LL 45 XXX X
Temperature grades: I = Industrial A = Auto-A Package type: BVX: VFBGA (Pb-free) ZSX: TSOP II (Pb-free) Speed grade Low power Voltage range = 3 V typical E = Process Technology 90 nm Bus Width = x16 Density = 16 Mbit 621 = MoBL SRAM family Company ID: CY = Cypress
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Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150-*E
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Figure 12. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
51-85183-*B
Acronyms
Acronym BHE BLE CMOS CE I/O OE SRAM TSOP VFBGA WE Description byte high enable byte low enable complementary metal oxide semiconductor chip enable input/output output enable static random access memory thin small outline package very fine ball grid array write enable
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Document History Page
Document Title: CY62167EV30 MoBL(R) 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 38-05446 Rev. ** *A ECN No. 202600 463674 Orig. of Change AJU NXR Submission Date 01/23/2004 See ECN Description of Change New Data Sheet Converted from Advance Information to Preliminary Removed `L' bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability. Changed ball E3 in FBGA pinout from DNU to NC Changed the ISB2(Typ) value from 1.3 A to 1.5 A Changed the ICC(Max) value from 40 mA to 25 mA Changed Vcc stabilization time in footnote #9 from 100 s to 200 s Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns. Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information. Updated the Ordering Information table Minor Change: Moved to external web Converted from preliminary to final Changed ICC max spec from 2.8 mA to 4.0 mA for f=1MHz Changed ICC typ spec from 22 mA to 25 mA for f=fmax Changed ICC max spec from 25 mA to 30 mA for f=fmax Added VIL spec for TSOP I package and footnote# 9 Added footnote# 10 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 A to 12 A Changed ICCDR spec from 8 A to 10 A Added footnote# 15 related to AC timing parameters Modified ICCDR spec for TSOP I package Added 48-Ball VFBGA (6 x 7 x 1mm) package Added footnote# 1 related to VFBGA (6 x 7 x 1mm) package Updated Ordering Information table Added Automotive-A information Included -45BVXA part in the Ordering information table Modified ICCDR spec from 8 A to 10 A for Auto-A grade. Added Contents. Updated all package diagrams. Updated links in Sales, Solutions, and Legal Information. Added footnote #25 related to chip enable. Updated template. Included BHE and BLE in ISB1, ISB2, and ICCDR test conditions to reflect Byte power down feature. Removed 48-Ball VFBGA (6 x 7 x 1 mm) package related information. Added Acronyms and Ordering code definition. Format updates to match template.
*B *C
469169 1130323
NSI VKN
See ECN See ECN
*D
1323984
VKN/AESA
See ECN
*E *F *G
2678799 2720234 2880574
VKN/PYRS VKN/AESA VKN
03/25/2009 06/17/2009 02/18/2010
*H *I
2934396 3006301
VKN RAME
06/03/10 08/12/2010
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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PSoC Solutions
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(c) Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05446 Rev. *I
Revised August 13, 2010
Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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